Verification of Stable Design in Final Design Check Iteration (Bug 2743)

The program was doing a full load distribution and wall d1.5” isesign during the final design check loop. The design check loop was intended to use the previous iteration's load distribution and designed walls to verify that the wall design / distribution achieved a stable design. By doing a full load distribution and wall design on the last iteration the verification check was not identifying when the wall design / load distribution does not achieve a stable design, and not issuing the appropriate warning. This has been corrected.